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Posted: Tuesday, April 18, 2017 1:18 PM

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This hands-on program presents to the students the design of digital integrated circuits using the Verilog digital design language as described in IEEE Standard 1364-2001. During the program, students will become familiar with the use of the Synopsys Design Compiler to synthesize gate-level netlists from behavioral, RTL, and structural Verilog code. The synthesis constraints most useful for area and speed optimization are emphasized. Almost all work is done in the synthesizable subset of the language; logic simulation is treated as an occasional verification method. Other topics include design partitioning, hierarchy decomposition, safe coding styles, assertion-based verification, and design for test.

We welcome and accept: Corporate Tuition Reimbursement, Workers Compensation, California Training Benefit (CTB), Trade Adjustment Act (TAA), Workforce Investment Act (WIA), Vocational Rehab, and more... For more information please contact Silicon Valley Polytechnic Institute; info@svpti.com or call 408-436-3000.

1762 Technology Dr.suite 228, 95110    google map | yahoo map

• Location: San Francisco, San Jose, Ca

• Post ID: 23943828 sf
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